1. Field of the Invention
Embodiments of the invention generally relate to manufacturing semiconductor, memory, solar, and other electronic devices, and more specifically, embodiments described herein relate to methods for fabricating and processing doped materials on a substrate surface.
2. Description of the Related Art
Flash memory, such as NAND flash memory devices, is a commonly used type of non-volatile memory in widespread use for mass storage applications. The NAND flash memory devices typically have a stacked type gate structure in which a tunnel oxide (TO), a floating gate (FG), an inter-poly dielectric (IPD), and a control gate (CG) are sequentially stacked on a semiconductor substrate. The floating gate, the tunnel oxide, and the underlying portion of the substrate generally form a cell (or memory unit) of the NAND flash memory device. A shallow trench isolation (STI) region is disposed in the substrate between each cell adjacent to the tunnel oxide and the floating gate to separate the cell from adjacent cells. During writing of the NAND flash memory devices, a positive voltage is applied to the control gate which draws electrons from the substrate into the floating gate. For erasing data of the NAND flash memory devices, a positive voltage is applied to the substrate to discharge electrons from the floating gate and through the tunnel oxide. The flow of electrons is sensed by a sensing circuitry and results in the returns of “0” or “1” as current indicators. The amount of electrons in the floating gate and “0” or “1” characteristics form the basis for storing data in the NAND flash memory devices.
The floating gate is typically isolated from the semiconductor substrate by the tunnel oxide and from the control gate by the inter-poly dielectric, which prevents the leakage of electrons between, for example, the substrate and the floating gate or the floating gate and the control gate. To enable continued development in physical scaling of the NAND flash memory device, a nitridation process has been used by the industry to incorporate nitrogen into the surface of the floating gate to improve the reliability of the tunnel oxide or to suppress dopant diffusion out of the floating gate. However, the nitridation process also undesirably incorporates nitrogen into shallow trench isolation regions. Nitrogen incorporated in the shallow trench isolation region between neighboring floating gate structures forms a charge leakage path which can negatively impact final device performance.
To insure good contact, and low sheet resistance, high level of dopants (e.g., about 1×1015 atoms/cm2 or greater) are desired in semiconducting materials, memory device materials, solar materials, and other electronic device materials. One major issue currently faced is dopant out-diffusion during anneal and activation. After dopants are implanted, for example by P3i or a beam-line process, a disordered and unactivated layer exists where many dopant atom lie in interstitial sites or near broken bonds. Typically, a thermal annealing process is used to both repair the damaged semiconductor and promote bond formation of the dopants substitutionally. Dopant requirements are near the solid solubility limits of the semiconductor/dopant system itself, the thermal anneals additional thermal budget often cause out-diffusion of dopants. One technique that may be used to minimize out-diffusion of dopants is to expose the doped material to a laser anneal in which the thermal budget is sufficiently small to minimize dopant diffusion. However, out-diffusion of dopants is often still a problem even after the laser anneal.
Therefore, there is a need for improved methods and for the stabilization of doped materials, such as the nitridation of nitridation of doped silicon or germanium materials.